Q:

What is the ADC maximum sampling rate?

A:

The ADC clock is limited to a maximum of 13 MHz. The ADC needs a minimum of 1 ADC clock cycle for acquisition plus 1 cycle per resolution bit. The maximum sampling rate is then dependent on the resolution bits:

12 bits => 1 cycle (acquisition) + 12 cycles (conversion) = 1 Msps

8 bits => 1 cycle (acquisition) + 8 cycles (conversion) = 1.44 Msps

6 bits => 1 cycle (acquisition) + 6 cycles (conversion)  = 1.86 Msps